1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a method of driving plasma display panel.
2. Description of the Related Art
Recently, a plasma display panel (hereinafter, referred to as “PDP”) has been the center of attention as a flat panel display since it is easy to be made into a large-sized panel. The PDP generally displays a picture by controlling the gas discharge period of each pixel in accordance with digital video data. Such a PDP includes three electrodes as in FIG. 1, and is typically an AC type of PDP which is driven by AC voltage.
FIG. 1 illustrates a magnified discharge cell that constitutes a general AC type PDP. A discharge cell 30 shown in FIG. 1 includes an upper plate having a scan electrode 12A, a sustain electrode 12B, an upper dielectric layer 14 and a protective film 16 which are sequentially formed on an upper substrate 10; and a lower plate having an address electrode 20, a lower dielectric layer 22, barrier ribs 24 and a phosphorus layer 26 that are sequentially formed on a lower substrate 18.
Each of the scan electrode 12A and the sustain electrode 12B includes a transparent electrode and a metal electrode that is for compensating the high resistance of the transparent electrode. The scan electrode 12A supplies a scan signal for address discharge and a sustain signal for sustain discharge. The sustain electrode 12B mainly supplies a sustain signal. The address electrode 20 is formed to cross the scan electrode 12A and the sustain electrode 12B. The address electrode 20 supplies a data signal for address discharge.
Electric charges generated by the discharge are accumulated at the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents the damage of the upper dielectric layer 14 caused by sputtering and increases the emission efficiency of secondary electrons. The dielectric layers 14, 22 and the protective film 16 enable to reduce the discharge voltage applied from the outside.
The barrier ribs 24 provide a discharge space together with the upper and lower substrates 10 and 18. And the barrier ribs 24 are formed in parallel to the address electrode 20 to prevent the ultraviolet ray generated by the gas discharge from leaking to adjacent cells.
The phosphorus layer 26 is spread over the surface of the lower dielectric layer 22 and the barrier ribs 24 to generate red, green and blue visible rays. The discharge space is fully filled up with an inert gas such as He, Ne, Ar, Xe, Kr, a mixture discharge gas of the above gases or an excimer gas that can generate ultraviolet ray by discharge, for gas discharge.
The discharge cell 30 of such a structure sustains the discharge in a surface discharge by the scan electrode 12A and the sustain electrode 12B after being selected as an opposite discharge by the address electrode 20 and the scan electrode 12A. Accordingly, a visible ray is emitted at the discharge cell 30 by having the phosphorus 26 emit light by the ultraviolet ray that is generated upon sustain discharge.
In case of this, the discharge cell 30 controls a sustain discharge period, i.e., the number of sustain discharge, in accordance with the video data to realize the gray scale required for image display. And, the color of one pixel is realized by compounding three discharge cells where each of red, green and blue phosphorus 26 is coated.
FIG. 2 illustrates a driving waveform of the related art PDP. As shown in FIG. 2, the PDP is driven in the manner of dividing one frame into an initialization period to initialize a full screen, an address period to select cells and a sustain period to sustain the discharge of the selected cells.
In the initialization period, a rising ramp waveform Ramp-up is simultaneously applied to all scan electrodes Y during a set-up interval SU. The rising ramp waveform Ramp-up causes a dark discharge within the cells of the full screen. The setup discharge causes positive wall charges to be accumulated in an address electrode X and a sustain electrode Z, and negative wall charges to be accumulated in a scan electrode Y.
During a set-down interval SD, a falling ramp waveform Ramp-down is applied to the scan electrodes Y. The falling ramp waveform Ramp-down falls from a positive voltage lower than a peak voltage of the rising ramp waveform Ramp-up up to the ground voltage GND or a specific negative voltage level, to thereby eliminate some of excessive wall charges formed within the cells. The wall charges to the extent that an address discharge might be stably generated are remained within the cells by the falling ramp pulse Ramp-down.
In the address period, a scan pulse Scan is sequentially applied to the scan electrodes Y and at the same time data pulses data synchronized with the scan pulses Scab are applied to the address electrodes X.
When the voltage difference between the scan pulse Scan and the data pulse data is added to the wall voltages generated in the initialization period, the address discharge is generated within the cell to which the data pulse data is applied. When sustain voltages are applied, wall charges to the extent that the discharge might be generated are formed within the cells selected by the address discharge.
A bias voltage Zdc is applied to the sustain electrode Z so as not to be generated a mis-discharge between the scan electrode Y and the sustain electrode Z by reducing a voltage difference between the sustain electrode Z and the scan electrode during the set-down interval SD and the address period.
In the sustain period, sustain pulses Sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the cells selected by the address discharge, a sustain discharge, i.e., display discharge, is generated between the scan electrode Y and the sustain electrode Z whenever each sustain pulse Sus is applied as the wall voltage within the cell is added to the sustain pulse Sus.
After the completion of the sustain discharge, a ramp waveform Ramp-era having a low pulse width and a low voltage level is supplied to the sustain electrode Z to erase the wall charge remaining within the cells.
FIG. 3 is a circuit diagram of the related art scan electrode driver. The scan electrode driver of the related art plasma display panel generates a rising ramp pulse Ramp-up and a falling ramp pulse Ramp-down in an initialization period.
First of all, a set-up switch Q5 and a seventh switch Q7 are turned on during the initialization period. At this time, a sustain voltage Vs is applied from a sustain pulse supplier 40. The sustain voltage Vs is supplied to scan electrodes via a body diode of a sixth switch Q6, the seventh switch Q7, and a scan IC 48.
In this case, since the sustain voltage Vs is applied to a negative terminal of a second capacitor C2, the second capacitor C2 supplies the sum(Vs+Vsetup) of the sustain voltage and the set-up volage to the fifth switch Q5.
The fifth switch Q5 supplies a voltage, having a predetermined inclination and applied from the second capacitor C2, to a first node point n1, by a first variable resistance VR1 and a third capacitor C2, which are installed at a previous stage of the fifth switch Q5.
The voltage, having the predetermined indication and applied to the first node point n1, is applied to the scan electrode via the seventh switch Q7 and the scan IC 48. Thus, the rising ramp pulse Ramp-up is applied to the scan electrodes.
After the rising ramp pulse Ramp0up is applied to the scan electrode, the fifth switch Q5 is turned off. If the fifth switch Q5 is turned off, then only Vs voltage supplied from the sustain pulse supplier 40 is applied to the first node point n1. Accordingly, voltages of the scan electrode and the sustain electrode fall to the Vs.
Thereafter, the seventh switch Q7 is turned off and a tenth switch 10 is turned on in the set-down interval SD. The tenth switch Q10 adjusts a channel width by a second variable resistance VR2 installed at a previous stage thereof, and falls a voltage of a second node n2, which the voltage has a predetermined inclination, to a writing scan voltage −V2. At this time, the falling ramp pulse Ramp-down is applied to the scan electrode.
However, in the related art driving waveform, a reset pulse of a high voltage is applied in a reset interval of each sub-field, so that a dark discharge is generated. Preferably, light should not be emitted in the reset interval. But, light is emitted due to the dark discharge caused by the reset pulse.
The generation of the light caused by the dark discharge is a main factor obstructing an improvement of contrast ratio of the plasma display panel, and a low contrast ratio reduces a distinctive degree of the plasma display panel.